Analog10y

PROBLEM 096 · Medium · The transmission gate

Both Ways

A transmission gate for a high input

The problem

Build a sampling switch for an input held at 1.5 V. An NMOS alone (gate on “clk”) loses its overdrive as the capacitor charges and stops near VDD − Vth − the voltage needed: it cannot pass 1.5 V in the time allowed. Add a PMOS in parallel with it whose gate is on “clkb” (the inverted clock, supplied by the test bench) so that the pair conducts over the whole input range.

A transmission gate has the NMOS pass low voltages and the PMOS high ones: the on-resistance of the pair stays small whatever the input. The capacitor starts at 0 V and the clock is high from 1 ns to 4 ns. Settle to within 5 mV of 1.5 V in under 1.5 ns.

The test bench

Numbers to hit

Design it yourself

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