Tick Tock

The problem

Build a switched-capacitor integrator. The test bench provides an op amp (terminals on the nets “inp”, “inn”, “out”; “inp” is at ground), an input held at 0.1 V on the net “in” and two non-overlapping clocks “phi1” and “phi2”. You supply a sampling capacitor C1 (1 pF) with a switch from “in” to its left plate and another from its right plate to ground on phi1, and switches from its left plate to ground and its right plate to “inn” on phi2, and a feedback capacitor Cf (2 pF) from “out” to “inn”. Use NMOS switches.

On phi1 C1 charges to Vin; on phi2 it dumps that charge into Cf: each clock cycle adds +Vin·C1/Cf to the output (the charge arrives with the opposite sign to the sample, which the op amp turns over). The result is an integrator, with an effective resistor of 1/(f·C1). Choose the capacitors so that each cycle steps the output up by 50 mV.

The test bench

• Supply: VDD = 1.8 V.
• The test bench provides the op amp (DC gain 80 dB, one pole at 100 kHz, output resistance 100 Ω; a 1 GΩ leak keeps its input biased), a 0.1 V input on “in”, and the clocks “phi1” (1 to 5 ns of every 10 ns) and “phi2” (6 to 10 ns). It runs 20 cycles and measures the average step of “out” per cycle.

Numbers to hit

• ◆Output step per clock cycle between 43 mV and 57 mV