Switch On

The problem

Build a sampling switch from one NMOS: its drain on “in” (held at 0.9 V by the test bench), its source on “out” (a 1 pF sampling capacitor to ground, also supplied by the test bench) and its gate on “clk” (a 0 to 1.8 V clock pulse from the test bench). The capacitor starts at 0 V.

While the clock is high the switch is a resistor Ron and the capacitor charges with a time constant Ron·C. When the clock falls, some of the channel charge flows into the capacitor and a gate–drain overlap capacitance couples the falling clock: the held voltage is slightly off. A wider switch has a smaller Ron but a larger charge to dump: you must pick the width that does both jobs.

The test bench

• Supply: VDD = 1.8 V.
• The test bench holds “in” at 0.9 V, drives “clk” high from 1 ns to 4 ns, and hangs a 1 pF capacitor from “out” to ground, starting at 0 V. It measures the settling time to within 1 mV of 0.9 V after the clock rises, and the step of “out” when the clock falls.

Numbers to hit

• ◆Settling time to 1 mV at most 1.5 ns
• ◆Step when the clock falls at most 40 mV