Charge Thief

The problem

Build a sampling switch from an NMOS (gate on “clk”) between “in” (held at 0.9 V by the test bench) and “out”, plus a dummy NMOS whose drain and source are both tied to “out” and whose gate is on “clkb” (the inverted clock, provided by the test bench). The dummy has half the switch’s width. Choose sizes so that the held voltage differs by less than 4 mV from the tracked one while the switch still settles within 1.5 ns.

When the main switch turns off, its channel charge splits between the two sides and the part that goes to the capacitor is an error. The dummy turns on at the same moment (its clock is the inverse): it takes up a charge of the opposite sign, cancelling the injection. The cancellation is best when the dummy’s area is half the switch’s, because only half of the switch’s charge reaches the capacitor.

The test bench

• Supply: VDD = 1.8 V.
• The test bench holds “in” at 0.9 V, drives “clk” high from 1 ns to 4 ns, provides “clkb” as its inverse, and hangs a 1 pF capacitor from “out” to ground (0 V at the start). It reports the settling time and the step of “out” when the clock falls.

Numbers to hit

• ◆Settling time to 1 mV at most 1.5 ns
• ◆Step when the clock falls at most 4 mV