PROBLEM 060 · Hard · Compensation at low power
Penny Pincher
A two-stage amplifier on 50 µW
The problem
This one is for a sensor node on a power budget of 50 µW. Build the two-stage Miller OTA: an NMOS pair with a PMOS mirror load and a tail from a bias mirror, a PMOS common-source second stage with an NMOS current-source load, and a series Rz + Cc compensation network from the first stage’s output to “out”. Mark the non-inverting input with an Input source named “inp”, the other gate with a Net label “inn”, and the output “out”.
Two poles are enough to make a loop unstable, so the point of this problem is where they fall. The first pole (the dominant one) is made low by Miller multiplication of Cc; the second sits at about gm2/C_L and must be well above the unity-gain frequency. The resistor Rz moves the right-half-plane zero.
The test bench
- Supply: VDD = 1.8 V.
- The test bench adds a 2p load capacitor on “out”, and a 1 GΩ feedback resistor from “out” to “inn” (with a 1 F capacitor from “inn” to a quiet source) so the amplifier biases itself but is open-loop for AC.
- It applies the AC stimulus to “inp” only.
Numbers to hit
- DC gain at least 60 dB
- Unity-gain bandwidth at least 3 MHz
- Phase margin at least 55 °
- Power at most 50 µW
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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