PROBLEM 055 · Medium · The Miller effect
Miller's Tax
The Miller effect on a common-source stage
The problem
Build a common-source amplifier fed by an Input source “in” through a 20 kΩ series resistor (the source resistance), with a resistor load from VDD to the drain “out” and a 100 fF capacitor from the drain to the gate (a stand-in for the transistor’s own Cgd, made bigger). Choose the transistor and the load so that the stage keeps at least 9.5 dB of gain and a bandwidth of 15 MHz or more.
The capacitor between drain and gate sees the whole voltage gain across it, so at the input it looks (1 + gain) times bigger: C_in ≈ Cgs + (1 + A)·Cgd. Together with the source resistance it makes an input pole at 1/(2π·Rs·C_in). More gain means more Miller capacitance: gain and bandwidth fight each other.
The test bench
- Supply: VDD = 1.8 V.
- The test bench hangs a 50 fF load capacitor from “out” to ground and applies the AC stimulus to “in”.
Numbers to hit
- Gain at least 9.5 dB
- Bandwidth (−3 dB) at least 15 MHz
- Output DC level between 0.7 V and 1.5 V
- Power at most 250 µW
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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