PROBLEM 056 · Medium · Zeros and bandwidth extension
Zero Hero
Bandwidth from a zero: the source RC network
The problem
Build a common-source amplifier with a degeneration network in the source: a resistor Rs in parallel with a capacitor Cs from the source to ground, a load resistor from VDD to the drain “out”, and the gate driven by an Input source “in”.
At low frequency Rs degenerates the stage and lowers the gain; at high frequency Cs short-circuits Rs and the full gm comes back. The result is a zero that raises the gain just as the output pole starts to cut it. Choose Cs so the zero lands near the output pole: the bandwidth grows several times, at the price of a lower DC gain.
The test bench
- Supply: VDD = 1.8 V.
- The test bench hangs a 200 fF load capacitor from “out” to ground and applies the AC stimulus to “in”.
Numbers to hit
- Low-frequency gain between 8 dB and 14 dB
- Bandwidth (−3 dB) at least 100 MHz
- Output DC level between 0.8 V and 1.5 V
- Power at most 250 µW
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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