PROBLEM 075 · Hard · Power-supply rejection
Ripple Blocker
Supply rejection of an LDO
The problem
Build the output stage of a low-dropout regulator. The test bench provides the control part: a 0.6 V reference and a high-gain error amplifier that compares the net “fb” with the reference and drives the net “gate”. You supply a PMOS pass transistor (source on VDD, gate on “gate”, drain on “out”) and a resistor divider from “out” to ground with its midpoint on “fb”. Choose the pass transistor and the divider so that supply ripple is attenuated by at least 55 dB at 1 kHz.
The error amplifier raises the gate voltage when the output is too high (so the PMOS conducts less) and lowers it when the output is too low. The loop holds “fb” at the reference: Vout = Vref·(1 + R1/R2). The pass transistor has to be large enough to carry the load current with a small drop across it.
The test bench
- Supply: VDD = 1.8 V.
- The test bench supplies the 0.6 V reference, an error amplifier (gain 10000) from “fb” to “gate”, a 1 µF output capacitor and a load current drawn from “out” to ground.
Numbers to hit
- Output at 5 mA between 1.1 V and 1.3 V
- Supply rejection at 1 kHz at least 55 dB
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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