Dropout Dare

The problem

Build the output stage of a low-dropout regulator. The test bench provides the control part: a 0.6 V reference and a high-gain error amplifier that compares the net “fb” with the reference and drives the net “gate”. You supply a PMOS pass transistor (source on VDD, gate on “gate”, drain on “out”) and a resistor divider from “out” to ground with its midpoint on “fb”. Choose the divider for 1.2 V and size the pass transistor so that the output stays in regulation until VDD falls to 1.4 V at a load of 5 mA.

The error amplifier raises the gate voltage when the output is too high (so the PMOS conducts less) and lowers it when the output is too low. The loop holds “fb” at the reference: Vout = Vref·(1 + R1/R2). The pass transistor has to be large enough to carry the load current with a small drop across it.

The test bench

• Supply: VDD = 1.8 V.
• The test bench supplies the 0.6 V reference, an error amplifier (gain 10000) from “fb” to “gate”, a 1 µF output capacitor and a load current drawn from “out” to ground.

Numbers to hit

• ◆Output at 1.8 V between 1.15 V and 1.25 V
• ◆Dropout voltage at 5 mA at most 250 mV
• ◆Every transistor in saturation