PROBLEM 078 · Hard · The NMOS pass regulator
Pass Master
An NMOS pass regulator: 0.8 V from 1.8 V
The problem
Build a series regulator with an NMOS pass transistor: drain on VDD, source on “out”, gate on the net “gate”. A resistor divider from “out” to ground has its midpoint on “fb”. The test bench provides a 0.4 V reference and an error amplifier whose output “gate” falls when “fb” rises. Choose the divider for an output of 0.8 V.
A follower pass device has a low output resistance (1/gm) and needs no compensation of its own, but its gate has to be about Vgs above the output: the output can never get closer to VDD than Vgs. The dropout voltage is the price. A wide transistor needs a small Vgs for the same current, which keeps the dropout small.
The test bench
- Supply: VDD = 1.8 V.
- The test bench supplies a 0.4 V reference, an error amplifier (gain 10000) from the reference minus “fb” to “gate”, a 1 µF output capacitor and a load current from “out” to ground, swept from 0.1 mA to 5 mA.
Numbers to hit
- Output at 1 mA between 0.75 V and 0.85 V
- Drop from 0.15 mA to 5 mA at most 15 mV
- Dropout voltage at 1 mA at most 900 mV
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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