PROBLEM 091 · Hard · A voltage-controlled oscillator
Starved
A current-starved VCO
The problem
Build a three-stage ring oscillator whose frequency depends on a control voltage “vctl”: each inverter’s NMOS has a second NMOS (the “starving” transistor, gate on “vctl”) in series with its source to ground. Name the first stage’s output net “n1”. The test bench supplies “vctl” (do not place a source) and measures the frequency at 0.8 V and at 1.2 V.
The starving transistor limits the current available to discharge each node, so a lower control voltage slows the ring. The frequency should at least double between 0.8 V and 1.2 V. The PMOS is not starved here, so the rising edge stays fast and the falling edge sets the frequency.
The test bench
- Supply: VDD = 1.8 V.
- The test bench holds “vctl” at 0.8 V, kicks “n1” with a short current pulse, simulates for 20 ns and measures the frequency; then repeats with “vctl” at 1.2 V.
Numbers to hit
- Frequency at vctl = 0.8 V at least 100 MHz
- Frequency at vctl = 1.2 V at least 400 MHz
- Tuning ratio f(1.2 V) / f(0.8 V) at least 2 ×
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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