PROBLEM 093 · Medium · The ring oscillator
Lucky Seven
A seven-stage ring near 400 MHz
The problem
Build a ring oscillator: 7 CMOS inverters in a loop, the output of each feeding the input of the next and the last feeding the first. Name the output nets “n1”, “n2”, …, “n7” (the output of the first stage is “n1”). Choose the transistor sizes for an oscillation frequency between 250 MHz and 600 MHz.
An odd number of inverting stages has no stable state: the signal chases itself round the loop. One trip round the loop through all the stages takes half a period (a rising edge goes round once to become a falling edge), so f = 1/(2·N·tp), where tp is the delay of one stage. Wider transistors drive their loads harder and speed up the ring, but also load the previous stage.
The test bench
- Supply: VDD = 1.8 V.
- The test bench injects a short current pulse into “n1” at 0.1 ns to start the oscillation, runs the simulator for ${Math.round((o.stop ?? 6e-9) * 1e9)} ns, and measures the frequency from the rising edges of “n1” after the first 2 ns, and the swing.
Numbers to hit
- Oscillation frequency between 250 MHz and 600 MHz
- Output swing at least 1.5 V
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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- Ring RingThree inverters in a loop and no input: a clock from nothing but delay.
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- Slow RingA ring of minimum inverters runs at several GHz. Hang a capacitor on each node to bring it down to a useful clock.
- Tank CircuitA tank, plus a pair of cross-coupled transistors that make a negative resistance to replace the energy it loses: the standard GHz oscillator.