PROBLEM 092 · Medium · Setting a frequency with capacitance
Slow Ring
A 200 MHz ring: slow it down with capacitors
The problem
Build a three-stage ring oscillator (outputs “n1”, “n2”, “n3”, the first stage’s output is “n1”) of inverters with a width of your choice, and add a capacitor from each ring node to ground so that the oscillation frequency falls between 150 MHz and 300 MHz.
The stage delay is C·VDD/(2·I) where C is the total capacitance on the node. The inverters’ own gate capacitance is a few femtofarads, so an added capacitor of a few hundred femtofarads dominates it and sets the frequency: f ≈ I/(6·C·VDD)·… in practice 1/(2·N·tp) with tp = 0.7·C·VDD/I.
The test bench
- Supply: VDD = 1.8 V.
- The test bench injects a short current pulse into “n1” at 0.1 ns, runs the simulator for 30 ns, and measures the frequency from the rising edges of “n1” after the first 6 ns.
Numbers to hit
- Oscillation frequency between 150 MHz and 300 MHz
- Output swing at least 1.5 V
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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