Fat Load

The problem

Build an NMOS common-source amplifier whose load is a PMOS biased as a current source: PMOS source on VDD, drain on “out”, gate held at a fixed DC voltage by an Input source named “vbp”. The amplifier’s input is an Input source named “in”, coupled to the NMOS gate through a 10 µF capacitor, and a 1 GΩ resistor from “out” to that gate biases the stage.

The stage has so much gain that nothing could set its output voltage by hand, so it biases itself: a 1 GΩ resistor from the output to the gate lets the DC level settle by feedback, and a 10 µF capacitor couples the AC input to the gate while keeping the source’s DC level out of the way. The resistor is so large that the feedback has no effect on the signal.

A current source has a high small-signal resistance (its ro), so the gain is gm/(gds_n + gds_p), tens of times more than a resistor load could give at the same current. Set “vbp” so that the PMOS carries about 50 µA.

The test bench

• Supply: VDD = 1.8 V.
• The test bench hangs a 200 fF load capacitor from “out” to ground and applies the AC stimulus to “in” only (“vbp” is not driven).
• Because the 10 µF capacitor blocks DC, set the “in” source to 0 V.

Numbers to hit

• ◆Gain at least 38 dB
• ◆Bandwidth (−3 dB) at least 2 MHz
• ◆Output DC level between 0.55 V and 1 V
• ◆Power at most 200 µW
• ◆Every transistor in saturation