PROBLEM 009 · Medium · CMOS common-source stage with an active load
Mid-Rail Rebel
Self-biased CMOS inverter amplifier
The problem
Build a CMOS inverter used as an amplifier: a PMOS and an NMOS with their gates joined, their drains joined as the output, the PMOS source on VDD and the NMOS source on ground. Both transistors amplify, so the gain is far larger than with a resistor load.
The catch is bias. A high-gain stage drifts to a rail unless its input rests at exactly the switching point. Tie a very large resistor (hundreds of megaohms or more) from the output back to the gate node, and feed the signal in through a capacitor, so the stage biases itself yet still passes the AC signal.
The test bench
- Supply: VDD = 1.8 V.
- The test bench hangs a 200 fF load capacitor on the net named “out”.
- The AC stimulus goes on the input source named “in”; its DC level is irrelevant to the amplifier because the capacitor blocks it (0 V is fine).
Numbers to hit
- Gain at 100 kHz at least 30 dB
- Unity-gain frequency at least 20 MHz
- Output DC level between 0.6 V and 1.2 V
- Power at most 30 µW
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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