Push & Pull

The problem

Build a push-pull output stage: an NMOS with its drain on VDD and its source on “out”, and a PMOS with its drain on ground and its source on “out”. The NMOS gate is on an Input source named “in” and the PMOS gate on a second Input source named “ip”; both receive the same AC signal, and their DC levels set how much current flows in the two transistors when nothing is asked of them (the quiescent current). The test bench hangs a 1 kΩ load from “out” to a 0.9 V source.

A single follower must carry the whole load current all the time, so its bias current is at least the largest current the load can ask for. In a push-pull pair each transistor carries current only in one direction: the quiescent current can be small while the stage still delivers milliamps at the peaks. The price is crossover: if both transistors are off the gain collapses, so the DC difference between the two gates must keep both slightly on.

The test bench

• Supply: VDD = 1.8 V.
• The test bench connects a 1 kΩ resistor from “out” to a 0.9 V source (so the load draws no DC current when “out” is at 0.9 V) and applies the same AC signal to “in” and “ip”.

Numbers to hit

• ◆Gain into 1 kΩ at least -2.5 dB
• ◆Output DC level between 0.8 V and 1 V
• ◆Power at most 800 µW