PROBLEM 072 · Hard · Why a gain stage needs a buffer
Gain & Carry
A gain stage with a buffer for a 1 kΩ load
The problem
Build a two-stage amplifier: a common-source NMOS (gate on the Input source “in”, a resistor from VDD to the drain) followed by a source follower (an NMOS with its gate on that drain, its drain on VDD, its source on “out”, biased by a Current source to ground). The test bench connects a 1 kΩ load from “out” to ground.
Without the follower the 8 kΩ load resistor and the 1 kΩ load would divide the signal by 9: the gain would collapse. The follower presents a high resistance to the first stage and a low one (1/gm) to the load, so the gain survives. The first stage’s output also sits one Vgs above the follower’s output, so the DC levels must be chosen with care.
The test bench
- Supply: VDD = 1.8 V.
- The test bench connects a 1 kΩ resistor from “out” to ground and applies the AC stimulus to “in”.
Numbers to hit
- Gain into 1 kΩ at least 6 dB
- Bandwidth (−3 dB) at least 20 MHz
- Output DC level between 0.3 V and 0.9 V
- Power at most 2500 µW
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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