PROBLEM 042 · Medium · Biasing a pair from a reference
Mirror Tail
A pair biased by a current mirror
The problem
Build a differential pair (two NMOS with load resistors to VDD) whose tail is an NMOS mirror. A 25 µA Current source from VDD feeds a diode-connected NMOS; the tail transistor has the same gate net, its source on ground, and four times the multiplier, so it draws 100 µA from the pair’s joined sources.
Mirrored tails are how real chips bias: one precise reference current is copied around the chip. Because the tail is a transistor, it has a finite output resistance, so make it long to keep the common-mode gain low.
The test bench
- Supply: VDD = 1.8 V.
- The test bench hangs a 200 fF load capacitor from each of “outp” and “outn” to ground and applies the AC stimulus to “inp” only.
Numbers to hit
- Tail current between 92 µA and 108 µA
- Differential gain at least 12 dB
- Output common-mode level between 0.8 V and 1.5 V
- Output DC imbalance at most 20 mV
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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- Two's CompanyTwo matched transistors share a tail current and turn a voltage difference into a differential output.
- Pair, FlippedFlip the pair upside down: PMOS inputs, a tail current from VDD, loads to ground. It works with inputs near ground.
- Tail RiskAn ideal tail current source rejects everything the inputs share. A transistor tail only does so if its output resistance is high.
- Slow DownAdd a resistor in each source: the gain drops, but the pair stays linear for a much larger input.
- LimboA pair only works while its tail transistor stays saturated. Find how much common-mode range your design really has.
- Load BearingUse PMOS diodes as the loads: the gain is no longer a resistor ratio but a transistor ratio.