PROBLEM 039 · Medium · Linearising a pair with source resistors
Slow Down
Source-degenerated differential pair
The problem
Build a differential pair with load resistors to VDD, a tail Current source and a resistor between each transistor’s source and the tail. Inputs “inp” and “inn”, outputs “outp” and “outn”, as before.
A plain pair’s transfer curve bends over (the tail current runs out) when the input is only about ±Vov/√2 from balance, 100 to 200 mV. A resistor in each source feeds the signal current back to the input, so the pair stays linear until the resistor’s drop is a sizeable fraction of the input: the linear range grows by (1 + gm·R). The price is gain, which falls by the same factor.
The test bench
- Supply: VDD = 1.8 V.
- The test bench hangs a 200 fF load capacitor from each output and applies the AC stimulus to “inp” only.
- It also sweeps the source “inp” from 0.4 V to 1.4 V (keeping “inn” fixed) and plots the differential output. The linear range is the input span over which the slope stays within 10% of its maximum.
Numbers to hit
- Differential gain between 4 dB and 12 dB
- Linear input range (within 10% of peak slope) at least 0.35 V
- Output common-mode level between 0.8 V and 1.5 V
- Output DC imbalance at most 20 mV
- Power at most 250 µW
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
Sign in or create a free account →More on differential pairs
- Two's CompanyTwo matched transistors share a tail current and turn a voltage difference into a differential output.
- Pair, FlippedFlip the pair upside down: PMOS inputs, a tail current from VDD, loads to ground. It works with inputs near ground.
- Tail RiskAn ideal tail current source rejects everything the inputs share. A transistor tail only does so if its output resistance is high.
- LimboA pair only works while its tail transistor stays saturated. Find how much common-mode range your design really has.
- Load BearingUse PMOS diodes as the loads: the gain is no longer a resistor ratio but a transistor ratio.
- Mirror TailReal tails come from mirrors. Take a 25 µA reference, scale it to 100 µA, and use it to bias the pair.