PROBLEM 088 · Hard · Systematic offset
Fair Fight
How balanced is your comparator?
The problem
Build a five-transistor OTA used as a comparator: an NMOS pair on a tail Current source with a PMOS mirror load (the input on the diode side is “inp”), output “out” at the drain of the mirror’s copy. The test bench holds “inn” at 0.9 V and sweeps “inp” around 0.9 V. The input-referred offset is the value of “inp” at which “out” sits at 0.9 V, minus 0.9 V.
A symmetric pair would have zero offset, but the mirror’s diode side sits at Vsg while the copy’s drain moves freely: the two PMOS see different drain voltages, so channel-length modulation unbalances their currents. The offset is the input difference needed to cancel it. Long, wide mirror transistors reduce it, as does a long channel in the pair.
The test bench
- Supply: VDD = 1.8 V.
- The test bench holds “inn” at 0.9 V and sweeps “inp” from 0.8 V to 1.0 V, then reports the input where “out” crosses 0.9 V. Do not place sources on “inp” and “inn”.
Numbers to hit
- Input-referred offset at most 15 mV
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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