PROBLEM 084 · Easy · Switching threshold and delay
Flip Point
A CMOS inverter: threshold at mid-supply, fast edges
The problem
Build a CMOS inverter: a PMOS with its source on VDD and an NMOS with its source on ground, both with their gates on the net “in” and their drains on the net “out”. The test bench drives “in” with a pulse: do not place a source on it.
The switching threshold is the input voltage at which the output equals the input. With equal widths the weaker PMOS pulls the threshold below mid-supply; making the PMOS wider by about the mobility ratio centres it. The speed of an edge is set by how much current the transistors can drive into the 50 fF load.
The test bench
- Supply: VDD = 1.8 V.
- The test bench drives “in” with a 0 to 1.8 V pulse (50 ps edges) and hangs a 50 fF load capacitor on “out”. It also sweeps “in” slowly from 0 V to 1.8 V to find the switching threshold: where “out” crosses 0.9 V.
Numbers to hit
- Switching threshold between 0.8 V and 1 V
- Falling-output delay at most 70 ps
- Rising-output delay at most 70 ps
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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