PROBLEM 032 · Medium · Bias for a cascode
Just Enough
A bias voltage for a cascode: Vgs plus a little
The problem
Build a bias generator for the gates of NMOS cascodes. A 20 µA Current source from VDD feeds the net “vc”. Two NMOS stacked from “vc” to ground produce it: the upper one with its gate and drain on “vc” and its source on the net “vm”; the lower one with its gate and drain on “vm” and its source on ground. Choose sizes so that “vm” is about 0.62 V (a plain Vgs at 20 µA) and “vc” about 1.4 V.
A cascode transistor’s gate needs to sit at about 2·Vgs: its own Vgs plus the voltage at its source, which is the Vgs of the transistor below it. Two diode-connected transistors in a stack give exactly that voltage, tracking the process and the temperature of the devices they bias. A narrow upper transistor raises Vgs and therefore “vc”.
The test bench
- Supply: VDD = 1.8 V.
- The Current source is the one you place: set it to 20 µA. The test bench reports the voltages of “vm” and “vc”.
Numbers to hit
- Voltage of “vm” (bottom Vgs) between 0.55 V and 0.7 V
- Voltage of “vc” (cascode gate bias) between 1.3 V and 1.5 V
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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