PROBLEM 045 · Expert · Two-stage op amps and frequency compensation
Miller Time
Two-stage Miller OTA
The problem
Build a two-stage operational transconductance amplifier. The first stage is an NMOS differential pair with a PMOS mirror load and a tail current source. The second stage is a PMOS common-source transistor whose gate is the first stage’s output, loaded by an NMOS current source. A current source and a diode-connected NMOS generate bias voltages for the tail and the second-stage load.
Two gain stages give far more gain than one, but two poles threaten stability. A Miller capacitor from the first stage’s output to the amplifier’s output splits the poles apart, and a resistor in series with it cancels the right-half-plane zero it creates. This is the circuit the ranked Problem 01 asks you to size: here you build it first.
Your “inp” gate is the first-stage transistor on the mirror’s output side; mark the other gate with a Net label named “inn”. Name the output “out”.
The test bench
- Supply: VDD = 1.8 V.
- The test bench adds a 2 pF load capacitor on “out”, and a 1 GΩ feedback resistor from “out” to “inn” (with a 1 F capacitor from “inn” to a quiet source) so the amplifier biases itself but is open-loop for AC.
- It applies the AC stimulus to the source named “inp”; set that source’s DC level yourself (0.9 V is a good common-mode).
Numbers to hit
- DC gain at least 60 dB
- Unity-gain bandwidth at least 20 MHz
- Phase margin at least 55 °
- Output DC level between 0.6 V and 1.3 V
- Power at most 300 µW
- Every transistor in saturation
Design it yourself
Draw the circuit on a schematic canvas, size every transistor, and see it simulated in your browser with ngspice and the SkyWater SKY130 models. Every transistor lights up green, gold or red by operating region as you move the sliders.
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